The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC manufacturing are needed.
For example, electron beam (e-beam) technology has been used in the manufacturing of semiconductor devices using maskless lithography. In one example, a computer controlled e-beam data pattern generator (DPG) is used to direct an incident e-beam towards a semiconductor substrate coated with a layer of electron-sensitive resist (a target). The exposed portions of the resist are then developed, leaving a patterned resist layer on the semiconductor substrate as a masking element for further lithographic processes. A typical e-beam DPG uses an array of mirrors to deflect the incident e-beam in forming a gray-scale raster image on the target. The image to be formed is represented using pixels in digital format. In view of large amount of image data to be presented to and processed by the e-beam DPG, lossless data compression and decompression are generally used. However, it has been difficult to achieve sufficient compression while providing a high decompression data rate for high-volume semiconductor manufacturing.